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? semiconductor components industries, llc, 2010 october, 2010 ? rev. 3 1 publication order number: ncp1252/d ncp1252 current mode pwm controller for forward and flyback applications the ncp1252 controller offers everything needed to build cost ? effective and reliable ac ? dc switching supplies dedicated to atx power supplies. thanks to the use of an internally fixed timer, ncp1252 detects an output overload without relying on the auxiliary vcc. a brown ? out input offers protection against low input voltages and improves the converter safety. finally a soic8 package saves pcb space and represents a solution of choice in cost sensitive project. features ? peak current mode control ? adjustable switching frequency up to 500 khz ? jittering frequency 5% of the switching frequency ? latched primary over current protection with 10 ms fixed delay ? delayed operation upon start ? up via an internal fixed timer ? adjustable soft ? start timer ? auto ? recovery brown ? out detection ? uc384x ? like uvlo thresholds ? vcc range from 9 v to 28 v with auto ? recovery uvlo ? internal 160 ns leading edge blanking ? adjustable internal ramp compensation ? +500 ma / ?800 ma source / sink capability ? maximum 50% duty cycle: a version ? maximum 80% duty cycle: b version ? maximum 65% duty cycle: c version ? ready for updated no load regulation specifications ? soic ? 8 package ? this is a pb ? free device typical applications ? power supplies for pc silver boxes, games adapter... ? flyback and forward converter soic ? 8 case 751 suffix d pin connections marking diagram (top view) offline controller http://onsemi.com 1 8 1252 = specific device code x = a, b or c version a = assembly location l = wafer lot y = year w = work week = pb ? free package 1252x alywx 1 8 see detailed ordering and shipping information in the package dimensions section on page 16 of this data sheet. ordering information ss v cc drv gnd fb bo cs rt 1
ncp1252 http://onsemi.com 2 vout ncp1252 vbulk vcc 1 2 3 4 8 6 7 5 100 nf* *minimum recommended decoupling capacitor value figure 1. typical application table 1. pin functions pin no. pin name function pin description 1 fb feedback this pin directly connects to an optocoupler collector. 2 bo brown ? out input this pin monitors the input voltage image to offer a brown ? out protection. 3 cs current sense monitors the primary current and allows the selection of the ramp com- pensation amplitude. 4 r t timing element a resistor connected to ground fixes the switching frequency. 5 gnd ? the controller ground pin. 6 drv driver this pin connects to the mosfet gate 7 v cc v cc this pin accepts voltage range from 8 v up to 28 v 8 sstart soft ? start a capacitor connected to ground selects the soft ? start duration. the soft start is grounded during the delay timer table 2. maximum ratings table (notes 1 and 2) symbol rating value unit v cc power supply voltage, vcc pin, transient voltage: 10 ms with i vcc < 20 ma 30 v v cc power supply voltage, vcc pin, continuous voltage 28 v i vcc maximum current injected into pin 7 20 ma maximum voltage on low power pins (except pin 6, 7) ? 0.3 to 10 v r j ? a ? so thermal resistance junction ? to ? air ? so8 180 c/w tj max maximum junction temperature 150 c storage temperature range ? 60 to +150 c esd capability, hbm model 1.8 kv esd capability, machine model 200 v stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above t he recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may af fect device reliability. 1. this device series contains esd protection and exceeds th e following tests: human body model 1800 v per jedec standard jesd22 ? a114e. machine model method 200 v per jedec standard jesd22 ? a115a. 2. this device contains latch ? up protection and exceeds 100 ma per jedec standard jesd78.
ncp1252 http://onsemi.com 3 bo + ? leb cs rsense s r q fs w s r q drv vcc management s hutdown (fc s) vbulk 15v boot strap 30 v grand reset bok uv lo r eset grand reset fb 2r r gnd ct active clamp 15v buffered ramp buffered ramp 3.5v 0v rr amp rcomp uvlo + ? vbo fa ul t ti me r count clock reset out vdd + ? vskip ibo hyst. jittering uv lo grand reset sst art iss vdd fi x e d delay 120 ms soft start rt fs w selection + ? 1v + ? fs wi ng soft start status s r q reset end set 10 khz clk 2 bits counter maxdc note: maxdc = 50% with a version maxdc = 80% with b version figure 2. internal circuit architecture rt vcc uvlo q q q reset maxdc = 65% with c version
ncp1252 http://onsemi.com 4 table 3. electrical charateristics (v cc = 15 v, r t = 43 k , c drv = 1 nf. for typical values t j = 25 c, for min/max values t j = ?25 c to +125 c , unless otherwise noted) characteristics test condition symbol min typ max unit supply section and v cc management startup threshold at which driving pulses are au- thorized v cc increasing v cc(on) 9.4 10 10.6 v minimum operating voltage at which driving pulses are stopped v cc decreasing v cc(off) 8.4 9 9.6 v hysteresis between v cc(on) and v cc(min) v cc(hys) 0.9 1.0 ? v start ? up current, controller disabled v cc < v cc(on) & v cc increasing from zero i cc1 ? ? 100 a internal ic consumption, controller switching f sw =100 khz, drv = open i cc2 0.5 1.4 2.2 ma internal ic consumption, controller switching f sw =100 khz, c drv = 1 nf i cc3 2.0 2.7 3.5 ma current comparator current sense voltage threshold v ilim 0.92 1 1.08 v leading edge blanking duration t leb ? 160 ? ns input bias current (note 3) i bias ? 0.02 ? a propagation delay from cs detected to gate turned off t ilim ? 70 150 ns internal ramp compensation voltage level @ 25 c (note 4) v ramp 3.15 3.5 3.85 v internal ramp compensation resistance to cs pin @ 25 c (note 4) r ramp ? 26.5 ? k internal oscillator oscillator frequency r t = 43 k & drv pin = 47 k f osc 92 100 108 khz oscillator frequency r t = 8.5 k & drv pin = 47 k f osc 425 500 550 khz frequency modulation in percentage of f osc (note 3) f jitter ? 5 ? % frequency modulation period (note 3) t swing ? 3.33 ? ms maximum operating frequency (note 3) f max 500 ? ? khz maximum duty ? cycle ? a version dc maxa 45.6 48 49.6 % maximum duty ? cycle ? b version dc maxb 76 80 84 % maximum duty ? cycle ? c version dc maxc 61 65 69 % feedback section internal voltage division from fb to cs setpoint fb div ? 3 ? ? internal pull ? up resistor r pull ? up ? 3.5 ? k fb pin maximum current fb pin = gnd i fb 1.5 ? ? ma internal feedback impedance from fb to gnd z fb ? 40 ? k open loop feedback voltage fb pin = open v fbol ? 6.0 ? v internal diode forward voltage (note 3) v f ? 0.75 ? v drive output drv source resistance r src ? 10 30 drv sink resistance r sink ? 6 19 output voltage rise ? time v cc = 15 v, c drv = 1nf, 10 to 90% t r ? 26 ? ns output voltage fall ? time v cc = 15 v, c drv = 1nf, 90 to 10% t f ? 22 ? ns 3. guaranteed by design 4. v ramp , r ramp guaranteed by design
ncp1252 http://onsemi.com 5 table 3. electrical charateristics (v cc = 15 v, r t = 43 k , c drv = 1 nf. for typical values t j = 25 c, for min/max values t j = ?25 c to +125 c , unless otherwise noted) characteristics unit max typ min symbol test condition drive output clamping voltage (maximum gate voltage) v cc = 25 v r drv = 47 k , c drv = 1 nf v cl ? 15 18 v high ? state voltage drop v cc = v cc(min) + 100 mv, r drv = 47 k , c drv = 1 nf v drv(clamp) ? 50 500 mv cycle skip skip cycle level v skip 0.2 0.3 0.4 v skip threshold reset v skip(reset) ? v skip + v skip(hy s) ? v skip threshold hysteresis v skip(hys) ? 25 ? mv soft start soft ? start charge current ss pin = gnd i ss 8.8 10 11 a soft start completion voltage threshold v ss 3.5 4.0 4.5 v internal delay before starting the soft start when v cc(on) is reached ss delay 100 120 155 ms protection current sense fault voltage level triggering the timer f cs 0.9 1 1.1 v timer delay before latching a fault (overload or short circuit) when cs pin > f cs t fault 10 15 20 ms brown ? out voltage v bo 0.974 1 1.026 v internal current source generating the brown ? out hysteresis ? 5 c t j +125c ? 25 c t j +125c i bo 8.8 8.6 10 10 11.2 11.2 a 3. guaranteed by design 4. v ramp , r ramp guaranteed by design typical characteristics figure 3. supply voltage threshold vs. junction temperature figure 4. supply voltage hysteresis vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 8.8 9.0 9.2 9.4 9.6 9.8 10.0 10.2 100 80 60 40 20 0 ? 20 ? 40 0.90 0.95 1.00 1.05 1.10 1.15 1.20 under voltage lock out level (v) supply voltage hysteresis level (v) 120 vcc(on) vcc(off) 120
ncp1252 http://onsemi.com 6 typical characteristics figure 5. start ? up current (i cc1 ) vs. junction temperature figure 6. supply current (i cc3 ) vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0 10 20 30 40 50 100 80 60 40 20 0 ? 20 ? 40 0 1 2 3 4 5 figure 7. supply current (i cc3 ) vs. supply voltage figure 8. current sense voltage threshold vs. junction temperature supply voltage vcc (v) temperature ( c) 30 25 20 15 10 0 1 2 3 4 120 80 60 40 20 0 ? 20 ? 40 0.92 0.94 0.96 0.98 1.00 1.04 1.06 1.08 figure 9. leading edge blanking time vs. junction temperature figure 10. leading edge blanking time vs. supply voltage temperature ( c) supply voltage vcc (v) 100 80 60 40 20 0 ? 20 ? 40 0 50 100 150 200 250 300 30 25 20 15 10 0 50 100 150 200 250 300 startup current icc1 ( a) supply current icc3 (ma) supply current icc3 (ma) current sense voltage threshold (v) leading edge blanking time (ns) leading edge blanking time (ns) 120 120 100 1.02 120
ncp1252 http://onsemi.com 7 typical characteristics figure 11. propagation delay from cs to drv vs. junction temperature figure 12. propagation delay from cs to drv vs. supply voltage temperature ( c) supply voltage vcc (v) 120 100 80 60 20 0 ? 20 ? 40 0 20 40 60 80 100 140 160 30 25 20 15 10 0 20 40 60 80 120 140 160 figure 13. oscillator frequency vs. junction temperature figure 14. oscillator frequency vs. supply voltage temperature ( c) supply voltage vcc (v) 120 80 60 40 20 0 ? 20 ? 40 92 94 96 98 100 104 106 108 30 25 20 15 10 92 94 96 98 100 104 106 108 figure 15. oscillator frequency vs. oscillator resistor figure 16. maximum duty ? cycle, a version vs. junction temperature rt resistor (k ) temperature ( c) 100 80 60 40 20 0 0 50 150 200 300 350 400 500 100 80 60 40 20 0 ? 20 ? 40 45 46 48 49 propagation delay (ns) propagation delay (ns) oscillator frequency @ rt = 43 k (khz) switching frequency, f sw (khz) maximum duty cycle (%) 120 40 100 102 100 102 oscillator frequency @ rt = 43 k (khz) 100 250 450 47 120
ncp1252 http://onsemi.com 8 typical characteristics figure 17. maximum duty ? cycle, b version vs. junction temperature figure 18. maximum duty ? cycle, c version vs. junction temperature temperature ( c) temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 76 77 78 79 80 82 83 84 100 80 60 40 20 0 ? 20 ? 40 0 2 4 6 8 10 12 14 figure 19. drive sink and source resistances vs. junction temperature figure 20. drive clamping voltage vs. junction temperature temperature ( c) supply voltage vcc (v) 100 80 60 40 20 0 ? 20 ? 40 10 12 14 16 20 30 25 20 15 10 10 12 14 16 18 20 figure 21. drive clamping voltage vs. supply voltage figure 22. skip cycle threshold vs. junction temperature temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 0 0.1 0.2 0.4 0.5 0.7 0.9 1.0 maximum duty cycle (%) drive sink and source resist- ance ( ) drive clamping voltage (v) drive clamping voltage (v) skip cycle threshold (v) 120 81 120 roh rol 120 18 0.3 0.6 0.8 120 temperature ( c) 100 80 60 40 20 0 ? 20 ? 40 61 62 63 64 65 67 68 69 maximum duty cycle (%) 120 66
ncp1252 http://onsemi.com 9 typical characteristics figure 23. soft start current vs. junction temperature figure 24. soft start completion voltage threshold vs. junction temperature temperature ( c) temperature ( c) 120 80 60 40 20 0 ? 20 ? 40 3.0 3.5 4.0 4.5 5.0 100 80 60 40 20 0 ? 20 ? 40 0.90 0.92 0.96 0.98 1.02 1.04 1.08 1.10 figure 25. brown out voltage threshold vs. junction temperature figure 26. brown out voltage threshold vs. supply voltage supply voltage vcc (v) temperature ( c) 30 25 20 15 10 0.90 0.92 0.94 0.98 1.02 1.04 1.08 1.10 100 80 60 40 20 0 ? 20 ? 40 8.0 8.5 9.0 9.5 10.0 11.0 11.5 12.0 figure 27. internal brown out current source vs. junction temperature supply voltage vcc (v) 30 25 20 15 10 8.0 8.5 9.0 9.5 10.5 11.0 11.5 12.0 soft start completion voltage threshold (v) brown out voltage threshold (v) brown out voltage threshold (v) internal brown out current source ( a) 100 0.94 1.00 1.06 120 0.96 1.00 1.06 120 10.5 internal brown out current source ( a) 10.0 figure 28. internal brown out current source vs. supply voltage temperature ( c) 120 80 60 40 20 0 ? 20 ? 40 8 9 10 11 soft start current ( a) 100
ncp1252 http://onsemi.com 10 application information introduction the ncp1252 hosts a high ? performance current ? mode controller specifically developed to drive power supplies designed for the atx and the adapter market: ? current mode operation: implementing peak current ? mode control topology, the circuit offers uc384x ? like features to build rugged power supplies. ? adjustable switching frequency: a resistor to ground precisely sets the switching frequency between 50 khz and a maximum of 500 khz. there is no synchronization capability. ? internal frequency jittering: frequency jittering softens the emi signature by spreading out peak energy within a band 5% from the center frequency. ? wide vcc excursion: the controller allows operation up to 28 v continuously and accepts transient voltage up to 30 v during 10 ms with i vcc < 20 ma ? gate drive clamping: a lot of power mosfets do not allow their driving voltage to exceed 20 v. the controller includes a low ? loss clamping voltage which prevents the gate from going beyond 15 v typical. ? low startup ? current: reaching a low no ? load standby power represents a difficult exercise when the controller requires an external, lossy, resistor connected to the bulk capacitor. the start ? up current is guaranteed to be less than 100 a maximum, helping the designer to reach a low standby power level. ? short ? circuit protection: by monitoring the cs pin voltage when it exceeds 1 v (maximum peak current), the controller detects a fault and starts an internal digital timer. on the condition that the digital timer elapses, the controller will permanently latch ? off. this allows accurate overload or short ? circuit detection which is not dependant on the auxiliary winding. reset occurs when: a) a bo reset is sensed, b) v cc is cycled down to v cc(min) level. if the short circuit or the fault disappear before the fault timer ends, the fault timer is reset only if the cs pin voltage level is below 1 v at least during 3 switching frequency periods. this delay before resetting the fault timer prevents any false or missing fault or over load detection. ? adjustable soft ? start: the soft ? start is activated upon a start ? up sequence (v cc going ? up and crossing v cc(on) ) after a minimum internal time delay of 120 ms (ss delay ). but also when the brown ? out pin is reset without in that case timer delay. this internal time delay gives extra time to the pfc to be sure that the output pfc voltage is in regulation. the soft start pin is grounded until the internal delay is ended. ? shutdown: if an external transistor brings the bo pin down, the controller is shut down, but all internal biasing circuits are alive. when the pin is released, a new soft ? start sequence takes place. ? brown ? out pr otection: bo pin permanently monitors a fraction of the input voltage. when this image is below the v bo threshold, the circuit stays off and does not switch. as soon the voltage image comes back within safe limits, the pulses are re ? started via a start ? up sequence including soft ? start. the hysteresis is implemented via a current source connected to the bo pin; this current source sinks a current (i bo ) from the pin to the ground. as the current source status depends on the brown ? out comparator, it can easily be used for hysteresis purposes. a transistor pulling down the bo pin to ground will shut ? off the controller. upon release, a new soft ? start sequence takes place. ? internal ramp compensation: a simple resistor connected from the cs pin to the sense resistor allows the designer to inject ramp compensation inside his design. ? skip cycle feature: when the power supply loads are decreasing to a low level, the duty cycle also decreases to the minimum value the controller can offer. if the output loads disappear, the converter runs at the minimum duty cycle fixed by the propagation delay and driving blocks. it often delivers too much energy to the secondary side and it trips the voltage supervisor. to avoid this problem, the fb is allowed to impose the min t on down to ~ v f and it further decreases down to v skip , zero duty cycle is imposed. this mode helps to ensure no ? load outputs conditions as requested by recently updated atx specifications. please note that the converter first goes to min t on before going to zero duty cycle: normal operation is thus not disturbed. the following figure illustrates the different mode of operation versus the fb pin level.
ncp1252 http://onsemi.com 11 fb level time normal operation: skip: dc = 0% figure 29. mode of operation versus the fb pin level dc min < dc < dc maxa/b/c v fbol = 6.0 v v f = 0.75 v v skip = 0.3 v operation @ t on_min dc = dc min startup sequence: the startup sequence is activated when vcc pin reaches v cc(on) level. once the startup sequence has been activated the internal delay timer (ss delay ) runs. only when the internal delay elapses the soft start can be allowed if the bo pin level is above v bo level. if the bo pin threshold is reached or as soon as this level will be reached the soft start is allowed. when the soft start is allowed the ss pin is released from the ground and the current source connected to this pin sources its current to the external capacitor connected on ss pin. the voltage variation of the ss pin divided by 4 gives the same peak current variation on the cs pin. the following figures illustrate the different startup cases. time bo pin time ss pin time drv pin time 120 ms: internal delay time bo pin time ss pin time drv pin time 120 ms: internal delay case #1 case #2 soft start soft start no pulse figure 30. different startup sequence case #1 & #2 v bo v cc(on) v cc pin v cc pin v bo v cc(on) with the case #1, when the v cc pin reaches the v cc(on) level, the internal timer starts. as the bo pin level is above the v bo threshold at the end of the internal delay, a soft start sequence is started. with the case #2, at the end of the internal delay, the bo pin level is below the v bo threshold thus the soft start sequence can not start. a new soft start sequence will start only when the bo pin reaches the v bo threshold.
ncp1252 http://onsemi.com 12 time time time time time bo pin time ss pin time drv pin time case #3 case #4 ss capacitor is discharged soft start figure 31. controller shuts down with the brown out pin v bo v cc(on) v cc pin bo pin ss pin drv pin v bo v cc(on) v cc pin when the bo pin is grounded, the controller is shut down and the ss pin is internally grounded in order to discharge the soft start capacitor connected to this pin (case #3). if the bo pin is released, when its level reaches the v bo level a new soft start sequence happens. soft start: as illustrated by the following figure, the rising voltage on the ss pin voltage divided by 4 controls the peak current sensed on the cs pin. thus as soon as the cs pin voltage becomes higher than the ss pin voltage divided by 4 the driver latch is reset. leb cs rse nse s r q rcomp clock uvlo grand reset ss iss vd d fixe d delay 120 ms soft start + ? soft start status drv 1/4 figure 32. soft start principle q
ncp1252 http://onsemi.com 13 the following figure illustrates a soft start sequence. soft start pin (2 v/div) cs pin (0.5 v/div) time (4 ms/div) figure 33. soft start example v ss = 4 v t ss = 13 ms brown ? out protection by monitoring the level on bo pin, the controller protects the forward converter against low input voltage conditions. when the bo pin level falls below the v bo level, the controllers stops pulsing until the input level goes back to normal and resumes the operation via a new soft start sequence. the brown ? out comparator features a fixed voltage reference level (v bo ). the hysteresis is implemented by using the internal current connected between the bo pin and the ground when the bo pin is below the internal voltage reference (v bo ). bo s r q shutdown vbulk bok uvlo r eset grand reset + ? vbo ibo rb o u p rb olo figure 34. bo pin setup q the following equations show how to calculate the resistors for bo pin. first of all, select the bulk voltage value at which the controller must start switching (v bulkon ) and the bulk voltage for shutdown (v bulkoff ) the controller. where: ? v bulkon = 370 v ? v bulkoff = 350 v ? v bo = 1 v ? i bo = 10 a when bo pin voltage is below v bo (internal voltage reference), the internal current source (i bo ) is activated. the following equation can be written: v bulkon r boup i bo v bo r bolo v bo (eq. 1) when bo pin voltage is higher than v bo , the internal current source is now disabled. the following equation can be written: v bo v bulkoff r bolo r bolo r boup (eq. 2) from equation 2 it can be extracted the r boup : r boup v bulkoff v bo v bo r bolo (eq. 3) equation 3 is substituted in equation 1 and solved for r bolo , yields:
ncp1252 http://onsemi.com 14 r bolo v bo i bo v bulkon v bo v bulkoff v bo 1 (eq. 4) r boup can be also written independently of r bolo by substituting equation 4 into equation 3 as follow: r boup v bulkon v bulkoff i bo (eq. 5) from equation 4 and equation 5, the resistor divider value can be calculated: r bolo 1 10 370 1 350 1 1 5731 r boup 370 350 10 2.0 m short circuit or over load protection: a short circuit or an overload situation is detected when the cs pin level reaching its maximum level at 1 v. in that case the fault status is stored in the latch and allows the digital timer count. if the digital timer ends then the fault is latched and the controller permanently stops the pulses on the driver pin. if the fault is gone before ending the digital timer, the timer is reset only after 3 switching controller periods without faul t detection (or when the cs pin < 1 v during at least 3 switching periods). if the fault is latched the controller can be reset if a bo reset is sensed or if v cc is cycled down to v cc(off) . cs pin (500 mv/div) 12 vout (5 v/div) time (4 ms/div) short circuit figure 35. short circuit detection example fault timer: 15 ms shut down there is one possibility to shut down the controller; this possibility consists at grounding the bo pin as illustrated in figure 34. ramp compensation ramp compensation is a known mean to cure subharmonic oscillations. these oscillations take place at half of the switching frequency and occur only during continuous conduction mode (ccm) with a duty ? cycle close to and above 50%. to lower the current loop gain, one usually injects between 50 and 100% of the inductor downslope. depicts how internally the ramp is generated: the ramp compensation applied on cs pin is from the internal oscillator ramp buffered. a switch placed between the buffered internal oscillator ramp and r ramp disconnects the ramp compensation during the off time drv signal.
ncp1252 http://onsemi.com 15 leb cs rsense s r q fb 2r r buffered ramp rramp rcomp clock vdd + ? drv path ccs figure 36. ramp compensation setup q in the ncp1252, the internal ramp swings with a slope of: s int v ramp dc max f sw (eq. 6) in a forward application the secondary ? side downslope viewed on a primary side requires a projection over the sense resistor r sense . thus: s sense (v out v f ) l out n s n p r sense (eq. 7) where: ? v out is output voltage level ? v f the freewheel diode forward drop ? l out , the secondary inductor value ? n s /n p the transformer turn ratio ? r sense : the sense resistor on the primary side assuming the selected amount of ramp compensation to be applied is comp , then we must calculate the division ratio to scale down s int accordingly: ratio r sense comp s int (eq. 8) a few line of algebra determined rcomp: r comp r ramp ratio 1 ratio (eq. 9) the previous ramp compensation calculation does not take into account the natural primary ramp created by the transformer magnetizing inductance. in some case illustrated here after the power supply does not need additional ramp compensation due to the high level of the natural primary ramp. the natural primary ramp is extracted from the following formula: s natural v bulk l mag r sense (eq. 10) then the natural ramp compensation will be: natural_comp s natural s sense (eq. 11) if the natural ramp compensation ( natural_comp ) is higher than the ramp compensation needed ( comp ), the power supply does not need additional ramp compensation. if not, only the difference ( comp ? natural_comp ) should be used to calculate the accurate compensation value. thus the new division ratio is: (eq. 12) if natural_comp comp ratio s sense ( comp natural_comp ) s int then r comp can be calculated with the same equation used when the natural ramp is neglected (equation 9). ramp compensation design example: 2 switch ? forward power supply specification: ? regulated output: 12 v ? l out = 27 h ? v f = 0.7 v (drop voltage on the regulated output) ? current sense resistor : 0.75 ? switching frequency : 125 khz ? v bulk = 350 v, minimum input voltage at which the power supply works. ? duty cycle max: dc max = 84% ? v ramp = 3.5 v, internal ramp level. ? r ramp = 26.5 k , internal pull ? up resistance ? targeted ramp compensation level: 100% ? transformer specification: ? l mag = 13 mh ? n s /n p = 0.085
ncp1252 http://onsemi.com 16 internal ramp compensation level s int v ramp dc max f sw s int 3.5 0.84 125 khz 520 mv s secondary ? side downslope projected over the sense resistor is: s sense (v out v f ) l out n s n p r sense s sense (12 0.7) 27
10 ? 6 0.085 0.75 29.99 mv s natural primary ramp: s natural v bulk l mag r sense s natural 350 13
10 ? 3 0.75 20.19 mv s thus the natural ramp compensation is: natural_comp s natural s sense natural_comp 20.19 29.99 67.3% here the natural ramp compensation is lower than the desired ramp compensation, so an external compensation should be added to prevent sub ? harmonics oscillation. ratio s sense ( comp natural_comp ) s int ratio 29.99
(1.00 0.67) 520 0.019 we can know calculate external resistor (r comp ) to reach the correct compensation level. r comp r ramp ratio 1 ratio r comp 26.5
10 3 0.019 1 0.019 509 thus with r comp = 510 , 100% compensation ramp is applied on the cs pin. the following example illustrates a power supply where the natural ramp offers enough ramp compensation to avoid external ramp compensation. 2 switch ? forward power supply specification: ? regulated output: 12 v ? l out = 27 h ? v f = 0.7 v (drop voltage on the regulated output) ? current sense resistor: 0.75 ? switching frequency: 125 khz ? v bulk = 350 v, minimum input voltage at which the power supply works. ? duty cycle max: dc max = 84% ? v ramp = 3.5 v, internal ramp level. ? r ramp = 26.5 k , internal pull ? up resistance ? targeted ramp compensation level: 100% ? transformer specification: ? l mag = 7 mh ? n s /n p = 0.085 secondary ? side downslope projected over the sense resistor is: s sense (v out v f ) l out n s n p r sense s sense (12 0.7) 27
10 ? 6 0.085 0.75 29.99 mv s the natural primary ramp is: s natural v bulk l mag r sense s natural 350 7
10 ? 3 0.75 37.5 mv s and the natural ramp compensation will be: natural_comp s natural s sense natural_comp 37.5 29.99 125% so in that case the natural ramp compensation due to the magnetizing inductance of the transformer will be enough to prevent any sub ? harmonics oscillation in case of duty cycle above 50%. table 4. ordering information device version marking shipping ? NCP1252ADR2G a version 1252a 2500/tape & reel ncp1252bdr2g b version 1252b 2500/tape & reel ncp1252cdr2g c version 1252c 2500/tape & reel ?for information on tape and reel specifications, including part orientation and tape sizes, please refer to our tape and reel packaging specification brochure, brd8011/d.
ncp1252 http://onsemi.com 17 package dimensions soic ? 8 nb case 751 ? 07 issue aj seating plane 1 4 5 8 n j x 45 k notes: 1. dimensioning and tolerancing per ansi y14.5m, 1982. 2. controlling dimension: millimeter. 3. dimension a and b do not include mold protrusion. 4. maximum mold protrusion 0.15 (0.006) per side. 5. dimension d does not include dambar protrusion. allowable dambar protrusion shall be 0.127 (0.005) total in excess of the d dimension at maximum material condition. 6. 751 ? 01 thru 751 ? 06 are obsolete. new standard is 751 ? 07. a b s d h c 0.10 (0.004) dim a min max min max inches 4.80 5.00 0.189 0.197 millimeters b 3.80 4.00 0.150 0.157 c 1.35 1.75 0.053 0.069 d 0.33 0.51 0.013 0.020 g 1.27 bsc 0.050 bsc h 0.10 0.25 0.004 0.010 j 0.19 0.25 0.007 0.010 k 0.40 1.27 0.016 0.050 m 0 8 0 8 n 0.25 0.50 0.010 0.020 s 5.80 6.20 0.228 0.244 ? x ? ? y ? g m y m 0.25 (0.010) ? z ? y m 0.25 (0.010) z s x s m 1.52 0.060 7.0 0.275 0.6 0.024 1.270 0.050 4.0 0.155 mm inches scale 6:1 *for additional information on our pb ? free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. soldering footprint* on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, af filiates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800 ? 282 ? 9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81 ? 3 ? 5773 ? 3850 ncp1252/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303 ? 675 ? 2175 or 800 ? 344 ? 3860 toll free usa/canada fax : 303 ? 675 ? 2176 or 800 ? 344 ? 3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative

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